Custom versus standard architectures for implementing speech coding algorithms

An application-specific integrated circuit (ASIC) for implementing low-delay speech coding algorithms is presented. The architecture consists of two types of arithmetic units: a variable number of adaptive arithmetic units (AAUs) connected in parallel and one distortion arithmetic unit (DAU). Each AAU contains an adaptive datapath which allows the units to perform various operations, such as filtering and inter product calculations, with a minimum of hardware. The DAU simplifies the codebook search for vector quantization by computing and comparing distortion measurements. The number of AAUs is optimized for power consumption and chip area. One efficient configuration consists of four AAUs. This configuration implements the lattice low-delay vector excitation coding algorithm with an estimated power consumption of less than 300 mW and area of 90 mm², which compares favorably with implementations on general-purpose digital signal processing (DSP) chips