DocumentCode
3430818
Title
RTL design validation, DFT and test pattern generation for high defects coverage
Author
Santos, M.B. ; Gonqalves, F.M. ; Teixeira, I.C. ; Teixeira, J.P.
Author_Institution
IST / INESC-id
fYear
2001
fDate
2001
Firstpage
99
Lastpage
105
Keywords
Arithmetic; Circuit faults; Circuit testing; Design for testability; Design methodology; Hardware design languages; Power system modeling; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 2001. IEEE European
ISSN
1530-1877
Print_ISBN
0-7695-1017-5
Type
conf
DOI
10.1109/ETW.2001.946672
Filename
946672
Link To Document