Title :
Area-time analysis of carry lookahead adders using enhanced multiple output domino logic
Author :
Wang, June ; Zhongde Wang ; Jullien, G.A. ; Miller, W.C.
Author_Institution :
VLSI Res. Group, Windsor Univ., Ont., Canada
fDate :
30 May-2 Jun 1994
Abstract :
In order to improve the area and speed of the design of carry lookahead adders (CLAs) using enhanced multiple output domino logic (EMODL), we investigate the trade-off between the number of cascaded gate stages and the gate fan-in of each stage by varying these factors in four different architectural structures for a 32-bit CLA implemented in 1.2 micron CMOS technology. HSPICE simulation results show that the number of cascaded stages is a more critical factor than the gate fan-in
Keywords :
CMOS logic circuits; SPICE; adders; carry logic; cascade networks; circuit analysis computing; logic CAD; multivalued logic circuits; 1.2 micron; 32 bit; CMOS technology; EMODL; HSPICE simulation; architectural structures; area-time analysis; carry lookahead adders; cascaded gate stages; enhanced multiple output domino logic; gate fan-in; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Delay; Logic design; Logic gates; MOSFETs; Timing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409196
