Title :
Design of Multiphase Decimation Filter IP Core in Software Radio Receiver
Author :
Yu, Donghai ; Wang, Ningchen ; Gui, Yijun
Author_Institution :
State Key Lab. of Millimeter Waves, Southeast Univ., Nanjing
Abstract :
This thesis introduces the design of multiphase decimation filter IP core in software radio receiver in detail. This soft-core could automatically generate Verilog-HDL code with optimized-structure according to input parameters. The application of this core can decrease the design time and cost, and improve reliability; it can also be combined with the dynamic reconfiguration FPGA technology to realize the aim that real-time changing filter performance in order to satisfy the flexible demand of software radio application system.
Keywords :
FIR filters; hardware description languages; radio receivers; software radio; FPGA technology; Verilog-HDL code; multiphase decimation filter IP core; software radio receiver; Application software; Costs; Field programmable gate arrays; Finite impulse response filter; Frequency conversion; Hardware design languages; Manufacturing; Receivers; Reconfigurable logic; Software radio;
Conference_Titel :
Wireless Communications, Networking and Mobile Computing, 2008. WiCOM '08. 4th International Conference on
Conference_Location :
Dalian
Print_ISBN :
978-1-4244-2107-7
Electronic_ISBN :
978-1-4244-2108-4
DOI :
10.1109/WiCom.2008.334
