A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications

Author

Takagi, Naofumi

Author_Institution

Dept. of Inf. Sci., Kyoto Univ., Japan

fYear

1991

fDate

26-28 Jun 1991

Firstpage

35

Lastpage

42

Abstract

A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient especially in applications, such as encryption/decryption in the RSA cryptosystem, where modular multiplications are carried out iteratively. Each subtraction for the division for residue calculation is embedded in the repeated multiply-addition. Numbers are represented in a redundant representation and addition/subtractions are performed without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature suitable for VLSI implementation

Keywords

VLSI; algorithm theory; cryptography; digital arithmetic; iterative methods; multiplying circuits; RSA cryptosystem; VLSI; bit slice feature; decryption; division; encryption; iterative modular multiplications; radix-4 modular multiplication hardware algorithm; redundant representation; regular cellular array structure; repeated multiply-addition; residue calculation; serial-parallel modular multiplier; subtraction; Algorithm design and analysis; Circuits; Cryptography; Hardware; Information science; Iterative algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Arithmetic, 1991. Proceedings., 10th IEEE Symposium on

Conference_Location

Grenoble

Print_ISBN

0-8186-9151-4

Type

conf

DOI

10.1109/ARITH.1991.145531

Filename

145531