The Design and Implementation of Reed-Solomon Decoder in Broadband Wireless Access

This paper introduces the broadband wireless access technology which is applied in WMAN. And the design of Reed-Solomon (RS (255, 239)) in IEEE802.16a/d FEC based on time-domain Berlekamp-Massey (BM) algorithm is implemented. In this decoder pipeline architecture is adopted. Furthermore, finite-field constant multipliers and specially the time-division- multiplex structure used for key equation solution are referred, which reduce the bulk of circuit and simplify the hardware architecture. The RS decoder has been synthesized with Design Compiler and 0.25 mum CMOS technology and the implementation result shows a scale of 24581 gates. The circuit can detect and correct at most 8 byte errors for each data frame under the demanded working frequency of 30 MHz, which meets the performance required on QAM demodulation chip.