High-speed multiplier design using multi-input counter and compressor circuits

The design of a fast multiplier implemented using either (7,3) parallel counter of (7:3) compressor circuits for implementation in CMOS technology is presented. It is shown that parallel multipliers implemented using (7,3) counters exhibit better performance than those implemented using (7:3) compressors. They exhibit identical delay characteristics while the counter implementation requires fewer gates and lays out better. Although the (7,3) counter implementation uses more gates than the Wallace and Dadda schemes, it achieves a lower delay. The (7,3) counter based implementation compares favorably with the (4:2) compressor implementation in terms of gate count, although it has slightly higher delay for the 16-b by 16-b multiplier example