DocumentCode :
3431317
Title :
The Alpha 21364 network architecture
Author :
Mukherjee, Shubhendu S. ; Bannon, Peter ; Lang, Steven ; Spink, Aaron ; Webb, David
Author_Institution :
Alpha Dev. Group, Compaq Comput. Corp., Shrewsbury, MA, USA
fYear :
2001
fDate :
2001
Firstpage :
113
Lastpage :
117
Abstract :
The Alpha 21364 processor provides a high-performance, highly scalable, and highly reliable network architecture. The router runs at 1.2 GHz and routes packets at a peak bandwidth of 22.4 GB/s. The network architecture scales up to a 128-processor configuration, which can support up to four terabytes of distributed Rambus memory and hundreds of terabytes of disk storage. The distributed Rambus memory is kept coherent via a scalable, directory-based cache coherence scheme. The network also provides a variety of reliability features, such as per-flit ECC. These features make the 21364 network architecture well-suited to support communication-intensive server applications
Keywords :
cache storage; computer networks; multiprocessing systems; protocols; reliability; Alpha 21364; Rambus memory; cache coherence; communication-intensive server applications; network architecture; per-flit ECC; reliability features; Artificial intelligence; Bandwidth; Clocks; Computer architecture; Delay; Microprocessors; Network servers; Random access memory; Telecommunication computing; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hot Interconnects 9, 2001.
Conference_Location :
Stanford, CA
Print_ISBN :
0-7695-1357-3
Type :
conf
DOI :
10.1109/HIS.2001.946702
Filename :
946702
Link To Document :
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