Development of a large-scale TEG for evaluation and analysis of yield and variation

We have developed the first TEG (Test Element Group) with large-scale patterns that compare well to those of an SoC; it also address decoders in its four corners. This TEG is based on the design rules of pure processes that are independent of the product. We have successfully measured pure process yield, failure terms, and failure locations. We evaluated characteristic chip variation, and performed stress tests. We verified the methodology for this TEG using five test chips with 100-nm physical gate lengths and five Cu interconnect layers that were fabricated using a 130-nm CMOS process. The developed TEG should become a strategic technology for measuring electrical dimension and charge-up damage and for analysis of database software.