System design and signal processing of optimized GPS SR receiver

In this paper, a high speed 12-channel real-time software GPS receiver is proposed. Firstly, the system architecture is presented and the block data processing mechanism is introduced. The SR receiver consists of a radio frequency (RF) front end, a data acquisition board, and software that runs on a laptop with a Pentium-M 1.5GHz processor running the Window^® XP operating system. The RF front end down converts the GPS signal to intermediate frequency (IF) signal and samples the IF signal at 16.368MHz. Then the optimized bit-wise algorithm is reviewed and the signal acquisition and tracking algorithm is described. The data acquisition board packs the 2-bit samples with a 2-bit in/8-bit out shift register and transfers the packed samples to laptop through a USB port. The software running on the laptop reads and processes 4 milliseconds of IF data at a time. The architecture and implementation of the SR receiver is described in this paper, including block data processing mechanism, optimized-bit wise parallel algorithm for correlation, signal acquisition, and tracking. Finally, the real-time performance of the SR receiver is also test and presented. It is shown that the software consumes about 40% Central Processing Unit (CPU) capacity when it tracking 12 satellites in real-time.