Tutorial IND2B: Structured Embedded Configuration and Test

Embedded infrastructure IP to optimize chip-level manufacturing test and debugging has become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This tutorial introduces a structured, standards-based approach to PCB self-test and FPGA configuration and presents how it can optimize manufacturing test and debugging, leverage ASIC level DFT, and support configurability, especially in today´s re configurable products. Today´s complex IC relies on scan and BIST for the majority of the test coverage achieved. Software driven functional self-test for PCBs and Systems now requires a solid foundation of scan-based self-test due to the complexity and skill required to achieve high fault coverage and useful diagnostics. Off-the-shelf infrastructure IP based on IEEE standards will enable system designers to build in the field re-configurable and high quality self-testable products with a minimum of engineering time and effort. Furthermore, the convergence of the FPGA configuration standard and scan-based test presents the designers new opportunities to increase fault coverage, lower their manufacturing test costs, field support costs, and extend their products´ useful life with in-the-field updates. Infrastructure IP for the board and system level will save engineering time and will reduce design risk since they are pre-engineered and leverage IEEE standards. The standards-based solutions are re-usable, from one phase of a single product life cycle to the next, and from one product design to the next