Title :
Synthesizing "Verification Aware" Models: Why and How?
Author :
Ganai, Malay K. ; Mukaiyama, Akira ; Gupta, Aarti ; Wakabayshi, Kazutoshi
Author_Institution :
NEC Labs. America, Princeton, NJ
Abstract :
Design-for-verification (DFV) methodology i.e., exporting designer\´s intent to verification tools has been quite effective in improving verification efforts. The authors take one step further in improving the verification efforts, by separating the design optimized for performance, area and power from the design optimized for correctness, thereby reducing the verification burden. The authors propose a new paradigm synthesis-for-verification (SFV) which involves synthesizing "verification-aware" designs that are more suitable for functional verification. SFV methodology should be applied along with DFV methodology to obtain the full benefit of verification efforts. Note, this SFV paradigm requires support only from automated synthesis approaches, e.g. high level synthesis (HLS), and can be easily automated. This is in contrast to DFV methodology, which requires designers\´ reliable insights. As part of SFV methodology, the authors first identify the effect of various design entities on the performance of model checkers. By guiding the use of such entities in existing behavioral synthesis techniques, the authors propose to obtain "verification friendly" models that are relatively easier to model check. The authors demonstrate effectiveness of such a paradigm using existing industry tools and designs
Keywords :
formal verification; high level synthesis; integrated circuit modelling; automated synthesis approaches; behavioral synthesis techniques; design-for-verification methodology; high level synthesis; synthesis-for-verification; verification aware models; verification friendly models; verification-aware designs; Bridges; Computer bugs; Design methodology; Design optimization; High level synthesis; Laboratories; National electric code; Power system modeling; Process design; Scalability;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.151