Study of wafer arcing on oxide etching process for advance VLSI technology

The MERIE mode back-end oxide etching process long time suffered arcing event. In etch process, arcing will induce film and metal line damages; and for the passivation/fuse etch process, arcing will result in visual defect. Both of these two arcing issue might increase the process cost due to yield loss and ruin of process chamber. In addition, the reliability concern, like wafer pin hole, was another issue when arcing occurred on wafers. In order to clarify the root cause of arcing occurred on the MERIE mode chamber for an back-end oxide etch process, detail studies of enhancement via the passivation/fuse arcing window were done in this paper.