Title :
Architecting Microprocessor Components in 3D Design Space
Author :
Vaidyanathan, Balaji ; Hung, Wei-Lun ; Wang, Feng ; Xie, Yuan ; Narayanan, Vijaykrishnan ; Irwin, Mary Jane
Author_Institution :
Pennsylvania Sate Univ., University Park, PA
Abstract :
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional (3D) chip architectures, with its intrinsic capability to reduce the wire length, is one of the promising solutions to mitigate the interconnect related issues. In this paper we implement a few components of a microprocessor using custom design to show the potential performance and power benefits achievable through 3D integration under thermal constraints. We also introduce a standard cell based 3D design flow which leverages the commercial 2D design tools. Using this design flow we provide performance results of wide range of arithmetic units in 3D, thus introducing a fast method to analyze the performance benefits of 3D designs. In contrast to prior work, which mostly investigates single components of a processor, our work takes multiple components into consideration and the experimental results are promising in terms of delay and power reductions. Complex designs in 3D that have equivalent performance compared to a simple 2D designs is taken for IPC improvement analysis. An IPC improvement of 11% shown for a microprocessor implemented in 2-strata 3D technology
Keywords :
integrated circuit design; logic design; microprocessor chips; 2D design tools; 3D design space; 3D integration; IPC improvement analysis; microprocessor components; thermal constraints; Arithmetic; Delay; Educational institutions; Energy consumption; Frequency; Integrated circuit interconnections; Microprocessors; Performance analysis; Random access memory; Wire;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.41