Architecture and Clock Programmable Baseband of an 800 MHz-6 GHz Software-Defined Wireless Receiver

Author

Bagheri, R. ; Mirzaei, A. ; Chehrazi, S. ; Abidi, A.A.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA

fYear

2007

fDate

6-10 Jan. 2007

Firstpage

135

Lastpage

140

Abstract

A software-defined radio receiver is designed from a low power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in today use a wideband RF front-end, including the low noise amplifier and a wide tuning-range synthesizer, spanning over 800 MHz-6 GHz is designed. The entire receiver circuits are implemented in 90 nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit tuning; clocks; discrete time filters; low noise amplifiers; low-power electronics; microwave receivers; programmable circuits; radio receivers; software radio; 0.8 to 6 GHz; 802.11g standards; 90 nm; CMOS technology; GSM standards; analog-to-digital converter; clock programmable baseband; clock-programmable discrete-time analog filters; low noise amplifier; low power ADC; software-defined radio receiver; software-defined wireless receiver; wide tuning-range synthesizer; wideband RF front-end; windowed integration sampler; Baseband; Broadband amplifiers; CMOS technology; Circuit noise; Clocks; Filters; Frequency synthesizers; Low-noise amplifiers; Radio frequency; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on

Conference_Location

Bangalore

ISSN

1063-9667

Print_ISBN

0-7695-2762-0

Type

conf

DOI

10.1109/VLSID.2007.42

Filename

4092035