Efficient complex-number multipliers mapped on FPGA

The use of the offset binary code (OBC) together with distributed arithmetic (DA) has been addressed by several authors as an area-efficient method to implement VLSI systems. In this paper is shown that it is not as efficient as if it is implemented on a FPGA. To verify that conclusion, two sets of digit-serial complex multipliers have been designed and implemented on FPGA. The first ones are only based on the DA technique and the second on OBC and DA. The results show that the first ones achieve better performance than the others and are more area-time efficient