Title :
Efficient implementation of tap delay line filter using high speed Digital Signal Processor
Author :
Akram, Muhammad Imran ; Sheikh, Asrar U H
Author_Institution :
Dept. of Electr. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
Abstract :
An efficient implementation of the linear Finite Impulse Response (FIR) Filter has been performed over the Texas Instrument (TI) TMS320C6416 fixed point Digital Signal Processor (DSP) platform. The implementation fully exploits the pipelined architecture of the processor along with the circular buffering to gain the speed factor of 7 times than the reference approach hence making this more suitable for high speed real-time signal processing applications involving tap delay line (TDL) model.
Keywords :
FIR filters; delay lines; digital signal processing chips; FIR filter; TDL model; Texas Instrument TMS320C6416 DSP platform; fixed point digital signal processor platform; high speed digital signal processor; high speed real-time signal processing; linear finite impulse response filter; pipelined architecture; tap delay line filter; Computer architecture; Delay lines; Digital signal processing; Finite impulse response filter; MATLAB; Real-time systems; Registers;
Conference_Titel :
Information Science, Signal Processing and their Applications (ISSPA), 2012 11th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0381-1
Electronic_ISBN :
978-1-4673-0380-4
DOI :
10.1109/ISSPA.2012.6310632
