Design of a visualization system of sequential logic chip based on SVG

With the development of large scale integrated circuit, the complexity of the chip has increased, and the analysis has become more difficult. This paper presents a new sequential logic chip analysis method-the state transition diagram visualization analysis method, which solves the low efficiency of traditional chip analysis method, and mainly describes design proposal and implementation procedure of visualization, and gives a way to analyze the security of sequential logic chips, and test the system with instances to verify the feasibility of the system.