An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis

The effect of variations (process, voltage, temperature, and crosstalk) on circuit delay is increasing with technology scaling. As a result, the timing uncertainty of clock signal is increasing. In this paper, an efficient methodology for clock timing uncertainty- and skew-aware clock tree synthesis and analysis is proposed. We first present a statistical and less pessimistic methodology (as compared to the traditional static timing analysis (STA) methodology) for computing the clock timing uncertainty under the impact of parameter variations (process, voltage, temperature, and crosstalk). We also devise a technique to synthesize a clock tree that has zero skew and on which uncertainty can be computed efficiently. Finally, using the proposed uncertainty analysis algorithm, a post-processing scheme to reanalyze the critical paths reported by traditional STA is presented. We applied our zero-skew tree synthesis algorithm on a real industrial design. With our analysis methodology, the worst-case timing uncertainty on this tree was reduced from 388ps (used by traditional STA tools) to 63ps