Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

With shrinking process node sizes, the inherent effect of process variations is playing an increasingly larger factor in defining the behavior of a circuit. Conventional static timing analysis (STA) using best case/worst case analysis (BC-WC) is overly pessimistic in many cases, and could also be optimistic in some cases. This has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. SSTA provides a robust and tractable framework where the variations of the process parameter space can be captured in one analysis and the results of the analysis can be used to predict the yield of the design (with respect to timing), along with other reports of interest such as the probability of a net being critical. A popular technique for SSTA is the first-order parameterized approach where sensitivities of the timing activities to process parameter variations are propagated through the circuit, and the probability distributions of timing activities are computed at points of interest based on these sensitivities. In this paper, we describe a methodology for taking into account the effect of input slew and output load sensitivities on path arrival sensitivities. In this paper we also describe how slew sensitivities can be propagated and provide analytical expressions for the same. We also provide experimental results to show the increase in accuracy obtained as compared with Monte-Carlo analysis