Design of A Fully Pipelined Single-Precision Multiply-Add-Fused Unit

The floating point multiply-add operation A+BtimesC is fundamental in many scientific and multimedia applications. This paper presents a fully pipelined single-precision multiply-add fused unit, which is based on the combination of the final addition with rounding. Normalization is performed before the final addition to determine the rounding position. A three-step normalization method is proposed for attaining latency reduction. Moreover, this paper presents a method to eliminate a one-bit error of the multiply result for increasing the precision. Finally, a new technique to deal with the number of 1, which is added in the LSB of the operand to get 2´s complement, is proposed to reduce logic complexity and time delay. The overall MAF unit has a latency of 5 cycles, a throughput of 1 cycle, and a cycle time of 1.82 ns in 0.18 mum CMOS technology