DocumentCode
3432605
Title
Novels clean methodology to improve GOI performance of high voltage device
Author
Shih, Yuh Jinn ; Tsai, Yong Feng ; Ku, Shao Yen ; You, Y.J.
Author_Institution
Taiwan Semicond. Manuf. Co. Ltd., Hsin-Chu, Taiwan
fYear
2002
fDate
10-11 Dec. 2002
Firstpage
264
Lastpage
266
Abstract
Dual gate technology is widely used on high voltage products. Therefore, the treatment on dual gate oxide loop is very critical. Unfortunately, some troubles happened at dual gate oxide loop process. Photoresist peeling and poor uniformity on LV gate oxide thickness were the major troubles on this loop. The intention of this report is to provide an optimized clean procedure at dual gate oxide loop for 0.35 HV device and improves GOI performance.
Keywords
cleaning; high-voltage techniques; photoresists; power integrated circuits; GOI properties; dual gate oxide loop; dual gate technology; high voltage device; novels clean methodology; photoresist peeling; Chemicals; Etching; Hafnium; Low voltage; Manufacturing industries; Resists; Rough surfaces; Semiconductor device manufacture; Silicon; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Manufacturing Technology Workshop, 2002
Print_ISBN
0-7803-7604-8
Type
conf
DOI
10.1109/SMTW.2002.1197443
Filename
1197443
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