DocumentCode
3432628
Title
Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding
Author
Balakrishnan, Kedarnath J.
Author_Institution
NEC Labs., Princeton, NJ
fYear
2007
fDate
Jan. 2007
Firstpage
345
Lastpage
350
Abstract
An efficient LFSR reseeding based scan vector compression scheme is proposed in this paper. By using a two step scheme of multiple small LFSRs and dictionary encoding of the LFSR seeds, very high compression can be achieved on scan load patterns. The proposed scheme involves reseeding only the required LFSRs depending on the number of specified bits in a scan load pattern thereby improving the encoding efficiency. Experiment results show that very high encoding efficiency can be achieved using the proposed scheme. Multiple small LFSRs are advantageous to a dictionary based compression scheme of the LFSR seeds. An algorithm to choose seeds intelligently to achieve higher second level compression is described. The proposed scheme can be used in both full built-in self-test (BIST) environments and hybrid-BIST environments where the compressed data is stored on the external test equipment. Experiments show that the proposed scheme requires less tester memory as compared to previously published results
Keywords
built-in self test; shift registers; LFSR reseeding; built-in self-test environment; compressed data; dictionary coding; efficient scan-based BIST; higher second level compression; hybrid-BIST environment; multiple LFSR; scan load patterns; scan vector compression scheme; Automatic testing; Built-in self-test; Data compression; Dictionaries; Encoding; Linear feedback shift registers; National electric code; Polynomials; Test equipment; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-2762-0
Type
conf
DOI
10.1109/VLSID.2007.71
Filename
4092069
Link To Document