Single-Symbol Parallel Interpolation in All-Digital Receiver

In this paper, a parallel interpolation structure for all-digital receiver is proposed. Unlike the existing serial interpolation method, which makes timing-adjustment for one sample at a time, the single-symbol parallel interpolation makes timing adjustment for one symbol at a time. This trait lightens the hardware-constraint to the processing rate of the interpolator, and in turn, improves the processing speed of the receiver. Besides, with a novel vector-type of fractional delay with overflow of elements, the parallel interpolation shows no performance loss compared to serial interpolation.