DocumentCode
3432997
Title
Current mirror test structures for studying adjacent layout effects on systematic transistor mismatch
Author
Tuinhout, H.P. ; Bretveld, A. ; Peters, W.C.M.
Author_Institution
Philips Res., Eindhoven, Netherlands
fYear
2003
fDate
17-20 March 2003
Firstpage
221
Lastpage
226
Abstract
This paper discusses a new current mirror based test structure that is used to identify and quantify systematic transistor mismatch degradation associated with layout features close to high precision current mirror transistors.
Keywords
BiCMOS integrated circuits; CMOS integrated circuits; analogue integrated circuits; current mirrors; integrated circuit layout; integrated circuit testing; mixed analogue-digital integrated circuits; transistor circuits; BiCMOS mixed signal system; CMOS mixed signal system; adjacent layout effects; analogue integrated circuit; current mirror test structures; current mirror transistors; layout features; mixed signal integrated circuit; systematic transistor mismatch; transistor mismatch degradation; Circuit testing; Consumer electronics; Electronic equipment testing; MOSFETs; Measurement standards; Mirrors; Semiconductor device testing; Signal processing; System testing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 2003. International Conference on
Print_ISBN
0-7803-7653-6
Type
conf
DOI
10.1109/ICMTS.2003.1197465
Filename
1197465
Link To Document