Dynamic accuracy adjustement for fixed width dividers

Divisions are needed in several signal processing applications and they are widely destined to hardware implementations. However, they often constitute the performance bottleneck because of the poor performances of the related large hardware dividers. We present a generic VLSI design to respond to some applications need of reducing dividers input width. Unlike any other published method, in our solution, the word´s width is dynamically adjusted while indicating which level of accuracy that is being processed. FPGA implementation results are provided to show our design´s low area and timing consumption to recover information that is always lost when usual Least Significant Bit (LSB) reduction is applied.