Title :
FPGA optimised 3-D cyclic convolution using dynamic partial reconfiguration
Author :
Krill, Benjamin ; Amira, Abbes ; Ahmad, Afandi
Author_Institution :
NIBEC, Univ. of Ulster, Newtownabbey, UK
Abstract :
This paper presents the design and implementation of a generic three-dimension (3-D) cyclic convolution (CC) on field programmable gate array (FPGA). Three CC calculation architectures have been proposed and integrated into the 3-D framework. Architectures using FPGA specific digital signal processor (DSP) and distributed arithmetic (DA) cores have been implemented on Xilinx Virtex-5 FPGAs. Experimental results and performance analysis of the area, power consumption, maximum frequency and throughput are covered in this paper. Finally, an evaluation of the generic CC has been carried out and reveals a significant trade-off of throughput and maximum frequency, whilst the DA implementation exhibits the reduction size of the read only memory (ROM) to store the precomputed values.
Keywords :
convolution; digital signal processing chips; field programmable gate arrays; performance evaluation; read-only storage; CC calculation architectures; DA cores; DSP; FPGA optimised 3D cyclic convolution; ROM; Xilinx Virtex-5 field programmable gate array; distributed arithmetic cores; dynamic partial reconfiguration; generic three-dimension cyclic convolution; performance analysis; power consumption; read only memory; reduction size; specific digital signal processor; Computer architecture; Convolution; Digital signal processing; Field programmable gate arrays; Hardware; Read only memory; Transforms;
Conference_Titel :
Information Science, Signal Processing and their Applications (ISSPA), 2012 11th International Conference on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4673-0381-1
Electronic_ISBN :
978-1-4673-0380-4
DOI :
10.1109/ISSPA.2012.6310696