Title :
LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability
Author :
Badrudduza, Sayeed A. ; Samson, Giby ; Clark, Lawrence T.
Author_Institution :
Dept. of Electr. Eng., Arizona State Univ.
Abstract :
Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stability when reading. The cell also resides in a low leakage, voltage collapsed, low standby power mode when not being accessed. The cell circuit topology, layout, and impact on memory design are described. Simulation of operation on 130 and 90 nm technologies and with predictive technology models for 65 and 45 nm technologies demonstrate the leakage reduction and measurement on 130 nm demonstrates improved read stability
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit layout; leakage currents; low-power electronics; nanotechnology; 130 nm; 45 nm; 65 nm; 90 nm; CMOS integrated circuits; SRAM; cell circuit topology; circuit layout; leakage controlled six-transistor static random access memory cell; memory design; read stability; CMOS integrated circuits; Circuit stability; Leakage current; Microprocessors; Predictive models; Random access memory; SRAM chips; Tunneling; Very large scale integration; Voltage;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.96
