DocumentCode
3433398
Title
Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique
Author
Viveka, K.R. ; Kawle, Abhilasha ; Amrutur, Bharadwaj
Author_Institution
CEDT, Indian Inst. of Sci., Bangalore
fYear
2007
fDate
6-10 Jan. 2007
Firstpage
638
Lastpage
646
Abstract
This paper presents design of a low power 256times72 bit TCAM in 0.13mum CMOS technology. In contrast to conventional match line (ML) sensing scheme in which equal power is consumed irrespective of match or mismatch, the ML scheme employed in this design allocates less power to match decisions involving a large number of mismatched bits. Typically, the probability of mismatch is high so this scheme results in significant CAM power reduction. We propose to use this technique along with pipelining of search operation in which the MLs are broken into several segments. Since most words fail to match in first segment, the search operation for subsequent segments is discontinued, resulting in further reduction in power consumption. The above architecture provides 70% power reduction while performing search in 3ns
Keywords
CMOS memory circuits; content-addressable storage; integrated circuit design; low-power electronics; 0.13 micron; CMOS technology; low power pipelined TCAM; match line sensing scheme; power allocation technique; power consumption; search operation; Associative memory; CADCAM; CMOS technology; Computer aided manufacturing; Data compression; Energy consumption; Internet; Multilevel systems; Pipeline processing; Spatial databases;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-2762-0
Type
conf
DOI
10.1109/VLSID.2007.99
Filename
4092114
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