Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA

The Wave Dynamic Differential Logic (WDDL) is a promising countermeasure to protect cryptographic devices from Differential Power Attacks (DPA). But the key challenge is to maintain symmetry between dual networks, so as to obtain equal propagation delays and power consumption on differential signals. In this paper, we deal with the problem of timing unbalance. We study the impact of different placement strategies on the delay unbalance in a Tree-based FPGA. In addition, we present a new timing-balance driven router which is based on the Pathfinder routing algorithm. Our placement and routing tools improve significantly the delay balance. In fact, the results obtained with WDDL DES netlist show that the average delay unbalance was reduced by 90%.