A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n⁺/p⁺ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below-GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the read/write performance, reduce standby leakage, and mitigate process (V_T) variability. The application of the technique to stacked read transistors in 8-T SRAM is also discussed.