A fast architecture for exhaustive search block matching algorithm with MPEG-4 applications

This paper presents a fast architecture for exhaustive search block matching algorithm (ESBMA). The proposed architecture has a SIMD structure with 31 processing elements (PEs). The proposed architecture has been prototyped, simulated and synthesized for the Xilinx Virtex II FPGA XC2V3000-4. It has a maximum clock frequency of 142.6 MHz that enables processing more than 41 4CIF frames per second. This prototyped architecture utilizes 40% of the register bits, 15% of the Block RAMs, and 54% of the LUTs in Xilinx Virtex II FPGA XC2V3000-4.