• DocumentCode
    3433504
  • Title

    Dual-MOSFET structure for suppression of kink in SOI MOSFETs at room and liquid helium temperatures

  • Author

    Gao, M.H. ; Colinge, J.P. ; Lauwers, L. ; Wu, S -H ; Claeys, C.

  • Author_Institution
    IMEC, Leuven, Belgium
  • fYear
    1990
  • fDate
    2-4 Oct 1990
  • Firstpage
    13
  • Lastpage
    14
  • Abstract
    The dual-MOSFET structure proposed consists of two SOI nMOSFETs, T 1 and T2, in series, but measured as a single device (T1 to the source and T2 to the drain) with a common gate electrode. The N+ region in between T1 and T2 is kept floating. This structure can confine the kink effect to the upper transistor T2 and thus successfully keeps the lower transistor T1 from undergoing pinch-off, impact ionization, and the kink effect. If the channel length of T1 is longer than that of T2, then T1 will dominate the overall output characteristics of the device. As a result, the kink effect is eliminated from the overall output characteristics. This structure can also confine the parasitic bipolar effect only to the upper transistor T2. Since the base hole current of T2 will recombine in the common N+ region, it cannot reach the base region of the lower transistor T 1. Results of measurements and simulation are given
  • Keywords
    impact ionisation; insulated gate field effect transistors; semiconductor-insulator boundaries; 300 K; 4.2 K; SOI MOSFET; Si-SiO2; dual-MOSFET structure; impact ionization; low temperature; nMOSFETs; parasitic bipolar effect; pinch-off; room temperature; simulation; suppression of kink; Circuit simulation; Electric breakdown; Electrodes; Helium; Impedance; MOS devices; MOSFET circuits; Stress; Temperature measurement; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOS/SOI Technology Conference, 1990., 1990 IEEE
  • Conference_Location
    Key West, FL
  • Print_ISBN
    0-87942-573-3
  • Type

    conf

  • DOI
    10.1109/SOSSOI.1990.145685
  • Filename
    145685