Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations

As technology scales to 40nm and beyond, intra-die process variability causes large delay and leakage variations across a chip in addition to expected die-to-die variations. In this paper, a new approach to post-manufacture circuit adaptation for yield maximization is proposed with special focus on the projected large intra-die variability of future CMOS technologies. Adaptation is achieved through an iterative implicit delay test (IDT) and reconfiguration procedure. The IDT is used to assess the timing of the circuit every time it is reconfigured until the best (with the lowest leakage) configuration, achievable within a specified reconfiguration time, is obtained. Since accurate delay testing is not possible at each step of the reconfiguration process, statistical correlation-based methods are used to determine the circuit timing. Reconfiguration is achieved by activating programmable gates that can be switched from a low-speed/low-leakage mode to a high-speed/high-leakage mode under digital control. The circuitry for self-adaptation is very simple, no external tester support is necessary and results show that a significant yield improvement is possible