Two-dimensional analytical threshold voltage model for nanoscale graded channel gate stack DG MOSFETs

Author

Abdi, M.A. ; Djeffal, F. ; Meguellati, M. ; Arar, D.

Author_Institution

Dept. of Electron., Univ. of Laghouat, Laghouat, Algeria

fYear

2009

fDate

13-16 Dec. 2009

Firstpage

892

Lastpage

895

Abstract

Due to the advancement of the oxide and channel materials engineering, nanoscale graded channel gate stack (GCGAS) Double Gate (DG) MOSFET has been investigated and expected to suppress the short-channel effects and improve the subthreshold performances. So, in this paper a new two-dimensional analytical threshold voltage model is proposed to study and improve of the behavior of the nanoscale DG MOSFET in subthreshold domain for nanoelectronics applications. The developed approaches are verified and validated by the good agreement found with the numerical simulation.

Keywords

MOSFET; nanoelectronics; semiconductor device models; double gate MOSFET; nanoelectronics; nanoscale DG MOSFET; nanoscale graded channel gate stack MOSFET; numerical simulation; short-channel effects; subthreshold domain; two-dimensional analytical threshold voltage model; Analytical models; Circuits; Doping; Gate leakage; High K dielectric materials; High-K gate dielectrics; MOSFETs; Permittivity; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Conference_Location

Yasmine Hammamet

Print_ISBN

978-1-4244-5090-9

Electronic_ISBN

978-1-4244-5091-6

Type

conf

DOI

10.1109/ICECS.2009.5410801

Filename

5410801