Title :
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture
Author :
Flanigan, Edward ; Adapa, Rajsekhar ; Cui, Hailong ; Laisne, Michael ; Tragoudas, Spyros ; Petrov, Tsvetomir
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL
Abstract :
This paper presents a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional function-based ATPG techniques alongside an implicit framework to efficiently identify testable PDFs under the LOC scan architecture, and avoids the complex backtracking performed by structural techniques which may abort PDF classifications for path intensive designs. The effectiveness and scalability of the proposed method is demonstrated on the path intensive ISCAS 89 benchmarks
Keywords :
automatic test pattern generation; boundary scan testing; delays; integrated circuit testing; ATPG; ISCAS 89; automatic test pattern generation; launch-off-capture scan; path delay faults; path intensive designs; Automatic test pattern generation; Circuit faults; Circuit testing; Data structures; Delay; Flip-flops; Frequency; Lab-on-a-chip; Noise robustness; Performance evaluation;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.86