Title :
VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition
Author :
Singh, Chitranjan K. ; Prasad, Sushma Honnavara ; Balsara, Poras T.
Author_Institution :
Erik Jonsson Sch. of Eng. & Comput. Sci., Texas Univ., Dallas, TX
Abstract :
Matrix inversion and triangularization problems are common to a wide variety of communication systems, signal processing applications and solution of a set of linear equations. Matrix inversion is a computationally intensive process and its hardware implementation based on fixed-point (FP) arithmetic is a challenging problem. This paper proposes a fully parallel VLSI architecture under fixed-precision for the inverse computation of a real square matrix using QR decomposition with modified Gram-Schmidt (MGS) orthogonalization. The MGS algorithm is stable and accurate to the integral multiples of machine precision under fixed-precision for a well-conditioned non-singular matrix. For typical matrices (4 times 4) found in MIMO communication systems, the proposed architecture was able to achieve a clock rate of 277 MHz with a latency of 18 time units and area of 72K gates using 0.18-mum CMOS technology. For a generic square matrix of order n, the latency required is 5n - 2 which is better than all previously known architectures. With the use of LUTs and log-domain computations, the total area has been reduced compared to architectures based on linear-domain computations
Keywords :
CMOS integrated circuits; MIMO communication; VLSI; fixed point arithmetic; matrix decomposition; matrix inversion; signal processing; table lookup; 0.18 micron; CMOS technology; LUT; MGS orthogonalization; MIMO communication; QR decomposition; VLSI architecture; fixed-point arithmetic; inverse computation; linear equations; log-domain computations; matrix inversion; modified Gram-Schmidt orthogonalization; signal processing; CMOS technology; Computer architecture; Concurrent computing; Delay; Equations; Fixed-point arithmetic; Hardware; Matrix decomposition; Signal processing; Very large scale integration;
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-7695-2762-0
DOI :
10.1109/VLSID.2007.177