DocumentCode :
3434040
Title :
Parallelization of DC Analysis through Multiport Decomposition
Author :
Trivedi, Gaurav ; Desai, Madhav P. ; Narayanan, H.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai
fYear :
2007
fDate :
Jan. 2007
Firstpage :
863
Lastpage :
868
Abstract :
Physical problems offer scope for macro level parallelization of solution by their essential structure. For parallelization of electrical network simulation, the most natural structure based method is that of multiport decomposition. In this paper this method is used for the simulation of electrical networks consisting of resistances, voltage and current sources using a distributed cluster of weakly coupled processors. At the two levels in which equations are solved in this method the authors have used sparse LU for both levels in the first scheme and sparse LU in the inner level and conjugate gradient in the outer level in the second scheme. Results are presented for planar networks, for the cases where the numbers of slave processors are 1 and 2, and for circuit sizes up to 8.2 million nodes and 16.4 million edges using 8 slave processors. The authors use a cluster of Pentium IV processors linked through a 10/100MBPS Ethernet switch
Keywords :
local area networks; microprocessor chips; network analysis; DC analysis; Ethernet switch; Pentium IV processors; distributed cluster; electrical network simulation; macro level parallelization; microprocessors; multiport decomposition; slave processors; sparse LU; Circuits; Computer networks; Concurrent computing; Costs; Diodes; Equations; Large-scale systems; Resistors; Switches; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Print_ISBN :
0-7695-2762-0
Type :
conf
DOI :
10.1109/VLSID.2007.125
Filename :
4092149
Link To Document :
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