Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization

In this paper, given a full-chip routing result with a set of rectilinear Steiner trees, based on the computation of critical areas for short and open wires, a two-phase timing-constrained yield-driven approach is proposed to minimize the critical area for short wires by using timing-constrained path reconstruction and minimize the critical area for open wires by using width-and timing-constrained wire sizing. The experimental results show that our proposed two-phase timing-constrained yield-driven approach increases about 8% ~ 12% chip yield for the tested benchmark examples in reasonable CPU time