DocumentCode
3434220
Title
Programmable Digital Frequency Multiplier
Author
Wadhwa, Sanjay K. ; Muhury, Deeya ; Thakur, Krishna
Author_Institution
Freescale Semicond. India Pvt. Ltd., Noida
fYear
2007
fDate
6-10 Jan. 2007
Firstpage
925
Lastpage
928
Abstract
A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in 90 nm CMOS process for input reference frequency of 32.768 KHz and multiplication factor range of 128 to 1023. The silicon results show less than 2% of average frequency error at maximum multiplication factor.
Keywords
CMOS integrated circuits; frequency multipliers; frequency stability; phase locked loops; programmable circuits; CMOS process; compensation mechanism; frequency 32.768 kHz; maximum multiplication factor; programmable digital frequency multiplier; Circuit stability; Clocks; Counting circuits; Equations; Frequency; Phase locked loops; Pulse generation; Silicon; Temperature; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2007. Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-7695-2762-0
Type
conf
DOI
10.1109/VLSID.2007.133
Filename
4092159
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