Low voltage CMOS active pixel sensor design methodology with device scaling considerations

Author

Shen, Chao ; Xu, Chen ; Weiquan ; Huang, R. ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2001

fDate

2001

Firstpage

21

Lastpage

24

Abstract

In this paper, the design methodology and trade-offs for low voltage CMOS active pixel sensors (APS) are studied. As a result of device scaling, the power supply voltage has to be scaled at the same time. However, with the conventional APS architecture, the swing available for analog to digital conversion is significantly reduced. A new architecture with PMOS reset transistor can increase the APS swing by one V_T (threshold voltage) at the expense of extra area required for the N-well. This extra area can be compensated by using transistors with reduced dimensions. The trade-off between area and power supply voltage over 4 generations of technologies is studied and compared

Keywords

CMOS image sensors; analogue-digital conversion; integrated circuit design; integrated circuit measurement; low-power electronics; power supply circuits; APS architecture; APS voltage swing; N-well area; PMOS reset transistor architecture; analog to digital conversion; design methodology; design trade-offs; device scaling; low voltage CMOS active pixel sensor design methodology; low voltage CMOS active pixel sensors; power supply voltage; power supply voltage scaling; threshold voltage; transistor dimensions; CMOS technology; Charge coupled devices; Design methodology; Dynamic range; Dynamic voltage scaling; Low voltage; MOS devices; Power supplies; Signal sampling; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2001. Proceedings. 2001 IEEE Hong Kong

Conference_Location

Hong Kong

Print_ISBN

0-7803-6714-6

Type

conf

DOI

10.1109/HKEDM.2001.946910

Filename

946910