DocumentCode
3434274
Title
Three dimensional hybrid wafer scale integration using the GE high density interconnect technology
Author
Wojnarowski, R.J. ; Fillion, R.A. ; Gorowitz, B. ; Saia, R.
Author_Institution
Gen. Electr. Co., Schenectady, NY, USA
fYear
1993
fDate
1993
Firstpage
309
Lastpage
317
Abstract
A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented.
Keywords
VLSI; hybrid integrated circuits; integrated circuit technology; multichip modules; 3D MCM; 3D hybrid WSI; HDI overlay technology; high density interconnect technology; interconnect; large distributed processing systems; multichip module; packaging; solid-state memory systems; three-dimensional multichip technology; very high density requirements; wafer scale integration; Circuit testing; Delay; Distributed processing; Integrated circuit interconnections; Packaging; Performance loss; Research and development; Solid state circuits; Substrates; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-0867-0
Type
conf
DOI
10.1109/ICWSI.1993.255247
Filename
255247
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