Title :
A 16×16-bit static CMOS wave-pipelined multiplier
Author :
Klass, Fabian ; Flynn, Michael J. ; Van de Goor, Ad J.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
fDate :
30 May-2 Jun 1994
Abstract :
A 16×16-bit wave-pipelined multiplier was designed using static CMOS. Wave pipelining is achieved by applying new data to the circuit faster than the propagation delay. The circuit has been fabricated in a 1.0 μm CMOS process and tested at 330-350 MHz, which is about 4 times faster than the maximum clock frequency without pipelining
Keywords :
CMOS logic circuits; multiplying circuits; pipeline arithmetic; 1 micron; 16 bit; 330 to 350 MHz; propagation delay; static CMOS multiplier; wave-pipelined multiplier; CMOS logic circuits; CMOS process; Circuit optimization; Circuit testing; Clocks; Logic circuits; MOSFETs; Pipeline processing; Propagation delay; Registers;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409217
