Title :
Effect of communication delay on gracefully degradable WSI processor array performance
Author :
Landis, David L. ; Nigam, Nitin
Author_Institution :
Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
Abstract :
Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.
Keywords :
VLSI; fault tolerant computing; microprocessor chips; parallel architectures; performance evaluation; WSI processor array performance; communication delay; degraded performance functional array; fault tolerant WSI processor array; interconnect length; maximum operating frequency; reconfiguration; soft switching; Clocks; Communication switching; Degradation; Delay effects; Fault tolerance; Frequency; Microelectronics; Performance analysis; Semiconductor device modeling; System performance;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255260
