The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays

Due to their operative nature, arithmetic and logic units (ALUs) are the most difficult functional circuits to check among the components of a processor. The efficient design of a 32-b strongly-fault-secure (SFS) ALU using a reduced Berger code is presented. The reduced Berger code encodes both operands and the computation results, and uses only the two least significant check bits of its Berger code counterpart regardless of information length. The application of reduced Berger code yields more efficient implementation of a strongly-fault-secure ALU than the previously proposed techniques.