Design flow for the generation of optimized FIR filters

This paper presents a design flow for the generation of optimized FIR filters. It includes a graphical interface to integrate the complete synthesis flow, from the filter specification to a synthesizable VHDL. This allows the user to quickly develop high performance filters that meet the design constraints. The designed software supports coefficient and data bit-width configuration at design time. The generated VHDL code is generic and can be synthesized using any logic synthesis tool. The generation tool employs a combination of the reduction of the coefficients to N-Power-of-Two (NPT) terms, where the maximum number of non-zeros in each coefficient is taken as a constraint, and two common subexpression elimination (CSE) algorithms to minimize the number of addition/subtraction operations used in the multiplier-less implementation of the filter. Synthesis results for a range of different filter specifications for both FPGA using Virtex 5 Pro device and TSMC 0,18um CMOS standard cell, using Cadence synthesis tool are presented.