• DocumentCode
    3434603
  • Title

    Lateral isolation in SOI CMOS technology

  • Author

    Haond, M.

  • Author_Institution
    CNET-CNS, Meylan, France
  • fYear
    1990
  • fDate
    2-4 Oct 1990
  • Firstpage
    117
  • Lastpage
    118
  • Abstract
    Silicon-on-insulator (SOI) technology has been the subject of intensive work, mainly because of the advantages related to its intrinsic isolation properties. This avoids such drastic problems as latchup, encountered in bulk submicron CMOS processes. A lateral isolation is however necessary for the separation of the different transistors. Two main approaches can be considered: field oxidation (LOCOS) or field silicon etching (mesa). The author presents a review of the advantages and problems related to these techniques for an application to a VLSI CMOS process
  • Keywords
    CMOS integrated circuits; etching; integrated circuit technology; oxidation; semiconductor-insulator boundaries; LOCOS; SOI CMOS technology; SiO2-Si; VLSI; etching; field oxidation; latchup; lateral isolation; mesa; review; transistors; CMOS process; CMOS technology; Etching; Impurities; Isolation technology; Leakage current; Oxidation; Silicon; Topology; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOS/SOI Technology Conference, 1990., 1990 IEEE
  • Conference_Location
    Key West, FL
  • Print_ISBN
    0-87942-573-3
  • Type

    conf

  • DOI
    10.1109/SOSSOI.1990.145737
  • Filename
    145737