Product/device reliability correlations for low-power applications

Summary form only given. Portable products such as cellular phones, laptop or tablet computers have critical power consumption limitations. Highly scaled 28nm CMOS technologies and beyond show high variability in process which impacts reliability. The high process, temperature and reliability variability pose significant power consumption challenges at product level. Power consumption at process corners can vary as much as 50%. In order to optimize high-speed logic circuit designs for low power needs, we need to accurately predict device to product aging across process, temperature and voltage corners. Understanding the impact of process and temperature variability on device/circuit aging and its correlation to product level reliability results is the focus of this talk. We compare the device/circuit aging for 28nm CMOS technology with SiON vs high-k gate dielectrics at different process corners SS, TT and FF. The talk offers insights into optimizing high performance designs at low power for portable product applications.