DocumentCode :
3434676
Title :
A new RC design for mixed-grain based dynamically reconfigurable architectures
Author :
Rhod, Eduardo ; Sterpone, Luca ; Carro, Luigi
Author_Institution :
Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear :
2009
fDate :
13-16 Dec. 2009
Firstpage :
984
Lastpage :
987
Abstract :
Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.
Keywords :
logic circuits; logic design; reconfigurable architectures; ALU implementation; CMOS technology; gate-level implementation; mixed-grain architecture; reconfigurable cell design; reconfigurable logic unit; size 0.18 micron; size 0.25 micron; size 0.35 micron; CMOS technology; Circuits; Computer architecture; Digital signal processing; Fabrics; Logic arrays; Performance analysis; Reconfigurable architectures; Reconfigurable logic; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
Type :
conf
DOI :
10.1109/ICECS.2009.5410843
Filename :
5410843
Link To Document :
بازگشت