DocumentCode
3434718
Title
3D wafer stack neurocomputing
Author
Campbell, Marie L. ; Toborg, S.T. ; Taylor, Scott L.
Author_Institution
Hughes Res. Lab., Malibu, CA, USA
fYear
1993
fDate
1993
Firstpage
67
Lastpage
74
Abstract
A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks.
Keywords
VLSI; backpropagation; feedforward neural nets; neural chips; parallel architectures; 3D wafer stack neurocomputing; MSIMD; cooperative vision integration; massively parallel architectures; microcode emulations; multilayer backpropagation; multiple-single-instruction multiple-data; neural network models; neural processing functions; three dimensional wafer scale integration; Acceleration; Backpropagation algorithms; Emulation; Multi-layer neural network; Neural network hardware; Neural networks; Packaging; Prototypes; Semiconductor device modeling; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-0867-0
Type
conf
DOI
10.1109/ICWSI.1993.255272
Filename
255272
Link To Document